Programs and synthesis data take the form of binary bits- 1s and 0s. Everything in the ROM is stored as a bit, which is data that can be in one of two states, either a 1 or a 0. The CPU reads this data as instructions on what to do next (a program), or as synthesis data to be assembled and ultimately turned into sound. The ROM and CPU exchange data using a digital signal with only two discrete levels- a high voltage representing a "1" and low voltage representing a "0". The simplest standard is 5V for High and 0V for Low. In contrast, an analog signal can be a voltage of any continuous amount- like 2.667V.
The CPU reads data in the ROM by sending an Address- it sends the ROM a 'house address' for where data 'lives'. For example, if the CPU inputs the 'house address' of "1001", the ROM will output whatever data 'lives' there- let's say, "10100". This example ROM would be organized into a 4x5 grid, with four rows for Address input, and five columns for Data output. Let's say the CPU inputs the address "1001" across the 4 Address lines. These four Bits are input simulataneously (in parallel); "1" on A1 (Address line 1), "0" on A2, "0" on A3, and "1" on A4. Likewise, the ROM outputs the data "10100" simultaneously; "1" on D1 (Data line 1), "0" on D2, "1" on D3, "0" on D4, "1" on D5.
What does it mean for a "0" or "1" to be 'on' an Address or Data line? The CPU inputs a "1" across Address line A1. This means the CPU drives a High signal of 5V across that line, and the ROM reads that as a "1". Simultaneously, the CPU drives a Low signal of 0V across A2, the ROM reads that as "0". The CPU also drives "0" and "1' across A3 and A4 respectively. Next, the ROM outputs data back to the CPU across the Data lines. The ROM drives a High signal of 5V across D1 and the CPU reads that as "1". Simultaneously, the ROM drives a Low signal of 0V across D2 and the CPU reads that as a "0". The ROM also drives "1", "0", "0" across D3, D4, D5, respectively.
The timing of these events is important for ROM bending. A CPU uses a clock, basically a very fast oscillator, that determines the speed at which events happen- the CPU can only perform actions when the clock ticks. When the CPU addresses the ROM on a clock tick, the address is driven across the Address lines, and on the same clock tick, the ROM drives the data across the Data lines. The ROM works almost instantaneously. This means that the address and data both appear on their lines at the same time.
Lastly, we must physically enable the ROM by supplying power to it. The ROM is connected to a V+ line at 5V and a Gnd (G) line at 0V.
So with the ROM powered, on a single clock tick: the CPU sends address to ROM, ROM sends data to CPU. Addresses are sent in parallel across Address lines A#, Data is sent in parallel across Data lines D#. Addresses and data take on one of two voltage levels, a High level representing a "1" and a Low level representing a "0".